Table-based DFM for accurate post-layout analysis
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United States of America Patent
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Jun 12, 2012
Grant Date -
Nov 24, 2011
app pub date -
Aug 2, 2011
filing date -
Oct 13, 2008
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Abstract
Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
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