Method and apparatus for approximating diagonal lines in placement
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United States of America Patent
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Jun 12, 2012
Grant Date -
Jan 3, 2008
app pub date -
Jun 16, 2006
filing date -
Jun 16, 2006
priority date (Note) -
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status (Latency Note)
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Abstract
Some embodiments of the invention provide a method for placing circuit modules in an integrated circuit (“IC”) layout. The method computes a placement metric for the IC layout. In some embodiments, computing the placement metric includes partitioning a region of the IC layout into several sub-regions by using a cut graph, where the cut graph is an approximation of a diagonal cut line. These embodiments then generate congestion-cost estimates by measuring the number of nets cut by the cut graph. In some embodiments, the cut graph is a staircase cut graph. These staircase cut graphs include several horizontal and vertical cut lines. In some embodiments, the cut graph is a cut arc.
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