Pattern decomposition method
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United States of America Patent
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Jun 26, 2012
Grant Date -
N/A
app pub date -
Oct 14, 2008
filing date -
Oct 14, 2008
priority date (Note) -
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Abstract
Some embodiments provide a method for decomposing a region of an integrated circuit (“IC”) design layout into multiple mask layouts. The method identifies a number of sets of geometries in the design layout region that must be collectively assigned to the multiple mask layouts. The method assigns the geometries in a first group of collectively-assigned sets to different mask layouts without splitting any of the geometries. The method assigns the geometries in a second group of the collectively-assigned sets to different mask layouts in such a way so as to minimize the number of splits in the geometries of the second group.
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