Nanostructured memory device
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United States of America Patent
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Jul 3, 2012
Grant Date -
Jun 16, 2011
app pub date -
Jul 2, 2009
filing date -
Jul 9, 2008
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The present invention provides a nanostructured memory device comprising at least one semiconductor nanowire (3) forming a current transport channel, one or more shell layers (4) arranged around at least a portion of the nanowire (3), and nano-sized charge trapping centers (10) embedded in said one or more shell layers (4), and one or more gate electrodes (14) arranged around at least a respective portion of said one or more shell layers (4). Preferably said one or more shell layers (4) are made of a wide band gap material or an insulator. The charge trapping centers (10) may be charged/written by using said one or more gate electrodes (14) and a change in an amount of charge stored in one or more of the charge trapping centers (10) alters the conductivity of the nanowire (3).
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