Memory controller device having timing offset capability
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United States of America Patent
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Jul 3, 2012
Issued Date -
N/A
app pub date -
May 29, 2007
filing date -
Apr 24, 2001
priority date (Note) -
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Abstract
A memory controller is disclosed. In one particular exemplary embodiment, the memory controller may comprise a first transmitter to output first and second write commands synchronously with respect to a clock signal, a second transmitter to output first data using a first timing offset such that the first data arrives at a first memory device in accordance with a predetermined timing relationship with respect to a first transition of the clock signal, and a third transmitter to output second data suing a second timing offset such that the second data arrives at a second memory device in accordance with a predetermined timing relationship with respect to a second transition of the clock signal.
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