Memory component having a write-timing calibration mode
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United States of America Patent
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Jul 10, 2012
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Sep 8, 2011
filing date -
Sep 15, 2004
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Abstract
In memory component having a write-timing calibration mode, control information that specifies a write operation is received via a first external signal path and write data corresponding to the write operation is received via a second external signal path. The memory component receives multiple delayed versions of a timing signal used to indicate that the write data is valid write data, and outputs signals corresponding to the multiple delayed versions of the timing signal to enable determination, in a memory controller, of a delay interval between outputting the control information on the first external signal path and outputting the write data on the second external signal path.
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