Interface processor

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8219789
APP PUB NO 20080229311A1
SERIAL NO

11717622

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Abstract

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The invention provides a processor comprising a first port operable to generate a first indication dependent on a first activity at the first port, and a second port operable to generate a second indication dependent on a second activity at the second port. The processor also comprises an execution unit arranged to execute multiple threads; and a thread scheduler connected to receive the indications and arranged to schedule the multiple threads for execution by the execution unit based on those indications. The scheduling includes suspending the execution of a thread until receipt of the respective ready signal. The first activity and the second activity are each associated with respective corresponding threads.

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Patent Owner(s)

Patent OwnerAddress
XMOS LIMITED5TH FLOOR ALDER CASTLE 10 NOBLE STREET LONDON EC2V 7QJ

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
May, Michael David Bristol, GB 32 628

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