
US Patent No: 8,222,939
Number of patents in Portfolio can not be more than 2000
Method and system for a glitch correction in an all digital phase lock loop
Stats
-
Jul 17, 2012
Issued date -
Jul 19, 2010
filing date -
12/838,754
serial no -
In Force
status
Importance
Abstract
The present invention relates to a method and system for glitch correction in an all digital phase lock loop. An all digital phase lock loop can include a phase error signal generation unit, a multi-phase oscillator, a glitch correction unit, and a phase to digital converter. The phase to digital converter receives a multi-phase signal from the multi-phase oscillator and generates a phase signal. The error signal generation unit receives the phase signal and a reference phase signal and generates a phase error signal, which is fed to the glitch correction unit. The glitch correction unit removes the glitches in the phase error signal by a portion of the phase error signal. The phase lock loop can also include a phase rotator and a calibration block. The calibration block instructs the phase rotator to rotate the multi-phase signal by the phase rotation which generates the minimum number of glitches.
First Claim
Related Publications
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
|
|
|||
| 2011/0057,738 Digitally Controlled Oscillators | 1 | 2009 | |
|
|
|||
| 7,907,023 Phase lock loop with a multiphase oscillator | 2 | 2009 | |
|
|
|||
| 2010/0033,220 ACCUMULATED PHASE-TO-DIGITAL CONVERSION IN DIGITAL PHASE LOCKED LOOPS | 2 | 2008 | |
|
|
|||
| 2009/0267,664 PLL CIRCUIT | 6 | 2008 | |
|
|
|||
| 7,158,596 Communication system and method for sending and receiving data at a higher or lower sample rate than a network frame rate using a phase locked loop | 3 | 2002 | |
|
|
|||
| 2008/0068,236 Adaptive spectral noise shaping to improve time to digital converter quantization resolution using dithering | 6 | 2007 | |
|
|
|||
| 6,738,922 Clock recovery unit which uses a detected frequency difference signal to help establish phase lock between a transmitted data signal and a recovered clock signal | 13 | 2000 | |
Patent Citation Ranking
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 3.5 Year Payment | $1600.00 | $800.00 | $400.00 | Jan 17, 2016 |
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Jan 17, 2020 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jan 17, 2024 |
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge - 3.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge - 7.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge - 11.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |