NAND flash memory programming

United States of America Patent

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Jul 17, 2012
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Mar 25, 2010
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Nov 30, 2009
filing date
Jul 28, 2006

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Abstract

A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages.

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Patent Owner	Address
U S BANK NATIONAL ASSOCIATION AS COLLATERAL AGENT	100 WALL STREET SUITE 1600 NEW YORK NY 10005

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G11C:STATIC STORES

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Inventor Name	Address	# of filed Patents	Total Citations
Aritome, Seiichi	Boise, US	291	8244
Li, Di	Boise, US	99	1029
Liu, Haitao	Meridian, US	376	1724

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NAND flash memory programming

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United States of America Patent

12627448

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PATENT NO	8223549
APP PUB NO	20100074021A1
SERIAL NO	12627448
DOCKET NO

US Family Size	Non-US Coverage
Patent Longevity	Forward Citations

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
July 17, 2012	US,8223549,B2 US8223549B2	GRANTED PATENT AS SECOND PUBLICATION
March 25, 2010	US,20100074021,A1 US20100074021A1	FIRST PUBLISHED PATENT APPLICATION

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12627448

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