Multiple level program verify in a memory device

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United States of America Patent

PATENT NO 8223555
APP PUB NO 20100284219A1
SERIAL NO

12436955

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Abstract

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Methods for multiple level program verify, memory devices, and memory systems are provided. In one such method, a series of programming pulses are applied to a memory cell to be programmed. A program verify pulse, at an initial program verify voltage, is applied to the memory cell after each programming pulse. The initial program verify voltage is a verify voltage that has been increased by a quick charge loss voltage. The quick charge loss voltage is subtracted from the initial program verify voltage after either a programming pulse has reached a certain reference voltage or a quantity of programming pulses has reached a pulse count threshold.

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Patent Owner(s)

Patent OwnerAddress
U S BANK NATIONAL ASSOCIATION AS COLLATERAL AGENT633 WEST FIFTH STREET 24TH FLOOR LOS ANGELES CA 90071

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
He, Deping Boise, US 61 120
Kessenich, Jeffrey Alan Boise, US 6 71
Kim, Taehoon Boise, US 198 1205

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