Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules
Number of patents in Portfolio can not be more than 2000
United States of America
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Aug 7, 2012
Issued Date -
N/A
app pub date -
Mar 14, 2011
filing date -
Mar 14, 2011
priority date (Note) -
Withdrawn
status (Latency Note)
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Abstract
A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector.
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