Semiconductor integrated circuit
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United States of America Patent
Stats
-
Aug 7, 2012
Grant Date -
Dec 2, 2010
app pub date -
May 19, 2010
filing date -
May 29, 2009
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The present invention is directed to lessen burden at the time of solving a conflict of overlapping processes in processes for a plurality of interruption factors. On completion of data transfer to an external memory, a data transfer completion interruption of high priority is generated. In the case where data transfer of predetermined number of packets is not completed in reception interruption, a timer interruption of low priority is generated. Before processing data in an external memory responding to the interruption, the number of transfer packets is obtained from a counter. After restart of reception, the counter stores the number of transfer restart packets. After obtaining the number of transfer packets from a counter responding to the occurrence of the timer interruption, a data transfer completion interruption is generated. According to the obtained number of transfer packets, execution of either a process responding to occurrence of the timer interruption or a process responding to occurrence of the data transfer completion interruption is omitted.
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