System and method for an asynchronous data buffer having buffer write and read pointers

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United States of America Patent

PATENT NO 8239607
APP PUB NO 20090319745A1
SERIAL NO

12553856

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Abstract

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A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A write pointer and a read pointer are monitored to provide a write-read pointer offset representing the timing between when read data is made available by the memory device and when the read data is retrieved by the memory controller. Based on the write-read pointer offset, adjustment to different timing parameters can be made.

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Patent Owner(s)

Patent OwnerAddress
U S BANK NATIONAL ASSOCIATION AS COLLATERAL AGENT100 WALL STREET SUITE 1600 NEW YORK NY 10005

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
LaBerge, Paul A Shoreview, US 112 2925

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