Reduction of memory latencies using fine grained parallelism and FIFO data structures
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United States of America Patent
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Aug 7, 2012
Grant Date -
Oct 28, 2010
app pub date -
Apr 24, 2009
filing date -
Apr 24, 2009
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Abstract
Software rendering and fine grained parallelism are utilized to reduce/avoid memory latency in a multi-processor (MP) system. According to one embodiment, the management of the transfer of data from one processor to another in the MP environment is moved into a low overhead hardware system. The low overhead hardware system may be a FIFO (“First In First Out”) hardware control. Each FIFO may be real or virtual.
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