Methods and apparatuses for improving reduced power operations in embedded memory arrays
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United States of America Patent
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Aug 14, 2012
Grant Date -
Jun 24, 2010
app pub date -
Dec 19, 2008
filing date -
Dec 19, 2008
priority date (Note) -
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Abstract
Methods and apparatuses are presented for improving reduced power operations in embedded memory arrays. Some embodiments may include a microprocessor, the microprocessor including at least one execution unit, a memory coupled to the execution unit, the memory including, a memory cell comprising a memory cell bus, a power circuit selectively coupling the memory cell bus to a first power plane and a second power plane, where the memory cell bus is coupled to the second power plane when the power circuit is substantially off, and a bit line pre-charge circuit coupled to the power circuit, where the power circuit selectively couples the first power plane to the pre-charge circuit for a predetermined period of time.
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