States encoding in multi-bit flash cells for optimizing error rate
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United States of America Patent
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Aug 14, 2012
Grant Date -
Feb 16, 2012
app pub date -
Sep 23, 2011
filing date -
Mar 14, 2004
priority date (Note) -
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Abstract
Memory cells are programmed and read, at least M=3 data bits per cell, according to a valid nonserial physical bit ordering with reference to a logical bit ordering. The logical bit ordering is chosen to give a more even distribution of error probabilities of the bits, relative to the probability distributions of the data error and the cell state transition error, than would be provided by the physical bit ordering alone. Preferably, both bit orderings have 2M−1 transitions. Preferably, the logical bit ordering is evenly distributed. The translation between the bit orderings is done by software or hardware.
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