Method of fabricating a deep trench insulated gate bipolar transistor

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United States of America Patent

PATENT NO 8247287
APP PUB NO 20120058607A1
SERIAL NO

13373210

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Abstract

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In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region.

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Patent Owner(s)

Patent OwnerAddress
POWER INTEGRATIONS INCSAN JOSE CA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Banerjee, Sujit San Jose, US 81 893
Parthasarathy, Vijay Mountain View, US 118 1383

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