Architecture and method for compensating for disparate signal rise and fall times by using polarity selection to improve timing and power in an integrated circuit
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 28, 2012
Issued Date -
N/A
app pub date -
Apr 2, 2010
filing date -
Sep 22, 2006
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method for reducing delay in an integrated circuit by compensating for differences in rise and fall delay times comprises creating a timing graph; computing minimum delay tuples for nodes in the timing graph; if there is not at least one feasible delay tuple, determining a longest path and computing minimum delay tuples for the longest path; changing polarities on the longest path to reduce delays; updating the timing graph by transferring new polarity and delay values; performing timing analysis to determine a new longest path if the new longest path is shorter than the prior longest path, accepting a resulting polarity selection and computing minimum delay tuples for the longest path; if the new longest path is not shorter than the prior longest path, accepting a resulting polarity selection and implementing changes in a user-program bitstream.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully