Memory controllers, memory systems, solid state drives and methods for processing a number of commands
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United States of America Patent
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Sep 4, 2012
Grant Date -
Jan 12, 2012
app pub date -
Sep 23, 2011
filing date -
Apr 9, 2009
priority date (Note) -
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Abstract
The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
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