Interface for prototyping integrated systems
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United States of America Patent
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Sep 4, 2012
Grant Date -
Aug 31, 2006
app pub date -
May 1, 2006
filing date -
Jun 6, 2003
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An interface is described which has at least one chip side port with a first plurality of pins for conveying fields of a packet and first and second circuit side ports each port having a set of pins with a lower number than the first set of pins in the chip side port. The interface is constructed so that interrupt signals from an off-chip circuit can be conveyed on-chip in a manner such that the interrupt signals are indistinguishable from interrupt signals received from on-chip modules connected to an on-chip communication path. The same principle is applicable to power-down signals.
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