Specialized processing block for programmable logic device
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United States of America Patent
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Sep 11, 2012
Grant Date -
Aug 9, 2007
app pub date -
Jun 5, 2006
filing date -
Feb 9, 2006
priority date (Note) -
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Abstract
A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.
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