High bandwidth memory interface
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United States of America Patent
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Sep 11, 2012
Grant Date -
Mar 13, 2008
app pub date -
Oct 3, 2007
filing date -
Jul 27, 1998
priority date (Note) -
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Abstract
A DRAM system configured for high bandwidth communication, the system includes at least one DRAM having resistive termination devices within the DRAM, and a controller connected to the DRAM through a data bus. The controller includes resistive termination devices and the data bus includes at least one clock line driven intermittently. The data bus provides write data from the controller to the DRAM, and provides read data from the DRAM to the controller.
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