Methods and systems for computer aided design of 3D integrated circuits
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United States of America Patent
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Sep 11, 2012
Grant Date -
Dec 22, 2011
app pub date -
Aug 26, 2011
filing date -
Jul 26, 2005
priority date (Note) -
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Abstract
Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.
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