Method and system for optimizing performance based on cache analysis
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United States of America Patent
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Sep 11, 2012
Grant Date -
Oct 11, 2007
app pub date -
Feb 22, 2006
filing date -
Feb 22, 2006
priority date (Note) -
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Abstract
Described is a method and system for optimizing a code layout for execution on a processor including internal and/or external cache memory. The method and system includes executing a program having a first layout, generating at least one memory access parameter for the program, the memory access parameter being based on a cache memory of a computing system on which the program is designed to run and constructing a second layout for the program as a function of the at least one memory access parameter.
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