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Abstract

A method for erasing a flash EEPROM memory device is disclosed. The memory device has a first semiconductor region of one conductivity type formed within a second semiconductor region of an opposite conductivity type, source and drain regions formed from a semiconductor layer of the opposite conductivity type in the first semiconductor region, a well electrode formed from a semiconductor layer of the conductivity type inside the first semiconductor region, a charge storing layer electrically isolated from the first semiconductor region by a dielectric layer and having electric charge retention properties, and a control gate electrode electrically isolated from the charge storing layer by a inter layer of coupling dielectrics. The method comprises the steps of: applying a first voltage bias to both the well electrode and the second semiconductor region and a second bias to the control gate electrode for a duration of F/N tunneling; applying a third voltage bias to the well electrode and the second semiconductor region and a first zero voltage bias to the control gate electrode for a duration of traps depopulation; and, after the duration of traps depopulation, applying a fourth voltage bias to the control gate electrode and a second zero voltage bias to the well electrode and the second semiconductor region for a duration of traps assisted tunneling.

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