Mitigation of flash memory latency and bandwidth limitations via a write activity log and buffer
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United States of America Patent
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Sep 25, 2012
Grant Date -
Aug 6, 2009
app pub date -
Feb 5, 2008
filing date -
Feb 5, 2008
priority date (Note) -
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Abstract
A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.
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