Hierarchical instruction scheduler facilitating instruction replay
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United States of America Patent
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Sep 25, 2012
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N/A
app pub date -
Oct 31, 2007
filing date -
Aug 29, 2005
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Abstract
A hierarchical instruction scheduler included in a hierarchical microprocessor comprising a plurality of execution clusters. In one embodiment, a hierarchical instruction scheduler comprises a first-level instruction scheduler configured to receive instructions for execution; store first operand status information for respective operands of the instructions; and dispatch the instructions to respective execution clusters based on the instructions' respective first operand status information. The instruction scheduler also includes a plurality of second-level instruction schedulers, each operatively coupled with the first-level instruction scheduler, each second-level instruction scheduler being included in a respective execution cluster The second-level instruction schedulers are each configured to receive instructions for execution from the first-level instruction scheduler; store second operand status information for respective operands of the instructions received from the first-level instruction scheduler; and dispatch instructions, for execution, to respective execution units of the execution clusters based on the instructions' respective second operand status information.
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