Wafer-level packaged device having self-assembled resilient leads
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United States of America Patent
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Oct 2, 2012
Grant Date -
Aug 18, 2011
app pub date -
Feb 17, 2010
filing date -
Feb 17, 2010
priority date (Note) -
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Abstract
A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.
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