Method of reducing coupling between floating gates in nonvolatile memory
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 16, 2012
Grant Date -
May 12, 2011
app pub date -
Jan 20, 2011
filing date -
Sep 21, 2006
priority date (Note) -
In Force
status (Latency Note)
Importance
Loading Importance Indicators... 
Abstract
A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.
Loading the Abstract Image...
OK
First Claim
Family
Loading Family data...
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully