FPGA simulated annealing accelerator
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 23, 2012
Grant Date -
Dec 24, 2009
app pub date -
Jun 22, 2009
filing date -
Jun 20, 2008
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Iterative repair problems are generally solved using a combinatorial search method such as simulated annealing are addressed with a FPGA-based coarse-grain pipelined architecture to accelerate a simulated annealing based iterative repair-type event scheduling application. Over 99% of the work done by any simulated annealing algorithm is the repeated execution of three high-level steps: (1) generating, (2) evaluating, and (3) determining the acceptability of a new problem solution. A pipelined processor is designed to take advantage of these steps.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully