Internal synchronization control for adaptive integrated circuitry
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United States of America Patent
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Oct 23, 2012
Grant Date -
Feb 17, 2005
app pub date -
Sep 9, 2004
filing date -
Aug 14, 2003
priority date (Note) -
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status (Latency Note)
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Abstract
The disclosure describes internal synchronization in adaptive integrated circuitry which utilizes a data flow model for data processing. Task initiation and execution are controlled based upon data consumption measured in data buffer units, with initiation of and transitions between tasks based on a determined boundary condition within the data stream. When a data processing task is selected for synchronization, a boundary condition in a data stream is determined for commencement of the selected data processing task. Then, a timing marker for the commencement of the selected data processing task is determined relative to the data stream. The timing marker is dual-valued, providing a designated buffer unit and a designated byte or bit location within the designated buffer. The timing marker is communicated to the selected data processing task, which then commences data processing at a location in the data stream designated by the timing marker.
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