Programmable packet processor with flow resolution logic
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United States of America Patent
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Oct 30, 2012
Grant Date -
Jun 17, 2010
app pub date -
Feb 16, 2010
filing date -
May 24, 2000
priority date (Note) -
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Abstract
A programmable packet switching controller has a packet buffer, a programmable packet classification engine and an application engine. The packet buffer stores inbound packets, and includes a header data extractor to extract header data from the inbound packets and store the extracted header data in a header data cache. The header data extractor also generates a header data cache index and provides it to the packet classification engine for it to retrieve the extracted header data. The application engine has a number of programmable sub-engines arrayed in a pipelined architecture. The packet classification engine provides start indicators based on the packet classification to the programmable sub-engines to identify application programs to be executed.
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