Power-saving method for Viterbi decoder and bit processing circuit of wireless receiver
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United States of America Patent
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Oct 30, 2012
Grant Date -
Aug 27, 2009
app pub date -
Dec 4, 2008
filing date -
Feb 22, 2008
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A power-saving method for Viterbi decoder and bit processing circuit of wireless receiver is provided. In response to various computational load of bit processing circuit and/or Viterbi decoder of a wireless receiver, the method is used for adjusting duty cycle of the bit processing circuit and/or the Viterbi decoder so as to save power in addition, in response to various data rates of the wireless receiver, the Viterbi decoder and the bit processing circuit are provided with power based on various duty cycles of related time pulse signals, thereby preventing the Viterbi decoder and/or the bit processing circuit from consuming power while being idle (during time segments of idle operation), so as to reduce power consumption.
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