Specialized processing block for programmable logic device
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United States of America Patent
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Oct 30, 2012
Grant Date -
N/A
app pub date -
Jun 5, 2006
filing date -
Feb 9, 2006
priority date (Note) -
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Abstract
A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for performing floating point operations. The floating point circuitry preferably includes rounding and normalization circuitry. To perform mantissa multiplications, the floating point circuitry preferably relies on the aforementioned multipliers of the specialized processing block.
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