Importance

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Abstract

Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. In an exemplary embodiment, a program operation of the memory circuit is performed on a first plurality of memory cells along a word-line, where the programming operation includes a series of alternating programming pulses and verify operations, with the memory cells individually locking out from further programming pulses as verified. The determination of whether the word-line is defective based on the number of programming pulses for the memory cells of a first subset of the first plurality to verify as programmed relative to the number of programming pulses for the memory cells of a second subset of the first plurality to verify as programmed, where the first and second subsets each contain multiple memory cells and are not the same.

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First Claim