Method and system for placing integrated circuits into predominantly ultra-low voltage mode for standby purposes
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United States of America Patent
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Nov 20, 2012
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N/A
app pub date -
Jul 29, 2011
filing date -
Jul 29, 2011
priority date (Note) -
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Abstract
A core logic portion of a clocked digital circuit is switched to be powered by a standby mode power voltage lower than a normal mode power voltage when the circuit is switched into a low power standby mode (LPSM). The standby mode power voltage is too low relative to normal ground to deterministically drive a transition logic portion of the circuit. However, a special ground bus (GNDx) is provided in the transition logic portion and that special ground bus (GNDx) is pulled down to a negative voltage below normal ground when the circuit is switched into the low power standby mode (LPSM).
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