Power control block with output glitch protection
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United States of America Patent
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Nov 20, 2012
Grant Date -
N/A
app pub date -
Apr 4, 2011
filing date -
Apr 4, 2011
priority date (Note) -
In Force
status (Latency Note)
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Abstract
Techniques are provided to reduce glitches at an output signal node when a device is switched to and from a low power operation mode. In one example, a method of operating a device includes providing power to operate a signal source of the device during a normal operation mode of the device. The method also includes passing an output signal from the signal source through a signal path to an output node during the normal operation mode. The method also includes receiving an operation mode signal to switch the device from the normal operation mode to a low power operation mode. The method also includes disabling the signal path to prevent glitches from appearing at the output node during the switch from the normal operation mode to the low power operation mode. The method also includes continuing providing power to the signal source until after the signal path is disabled.
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