Providing a feedback loop in a low latency serial interconnect architecture

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United States of America

PATENT NO 8314724
SERIAL NO

12969249

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Abstract

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In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Benhamou, Assaf Haifa, IL 13 27
Lazar, Dror Kiryat Bialik, IL 9 41
Shoor, Ehud Haifa, IL 18 145

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