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Abstract

A method for testing a primary memory of control and regulation electronics of a frequency converter is described. The primary memory includes (i) at least one matrix of memory cells, (ii) means for addressing the at least one memory cell matrix, and (iii) a write/read circuit The method includes examining at least a part of the means for addressing with regard to address errors and examining at least a part of the memory cells with regard to cell errors. The examining steps are performed independently of one another. The examining at least a part of the means for addressing includes examining individual address bits of an n-bit wide address bus in steps that are performed independently of one another. The examining is dependent on use of the primary memory for operation of the frequency converter.

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