Three dimensional structure memory
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United States of America Patent
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Nov 27, 2012
Grant Date -
Sep 3, 2009
app pub date -
Mar 17, 2009
filing date -
Apr 4, 1997
priority date (Note) -
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Abstract
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
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