Importance

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Abstract

A gate dielectric functioning as a charge-trapping layer of a non-volatile memory cell with a structure of an insulator gate field effect transistor is formed by laminating a first insulator formed of a silicon oxide film, a second insulator formed of a silicon nitride film, a third insulator formed of a silicon nitride film containing oxygen, and a fourth insulator formed of a silicon oxide film in this order on a main surface of a semiconductor substrate. Holes are injected into the charge-trapping layer from a gate electrode side. Accordingly, since the operations can be achieved without the penetration of the holes through the interface in contact to the channel and the first insulator, the deterioration in rewriting endurance and the charge-trapping characteristics due to the deterioration of the first insulator does not occur, and highly efficient rewriting (writing and erasing) characteristics and stable charge-trapping characteristics can be achieved.

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First Claim