Clocked memory system with termination component
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United States of America Patent
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Nov 27, 2012
Grant Date -
Oct 25, 2007
app pub date -
Jun 25, 2007
filing date -
Apr 24, 2001
priority date (Note) -
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Abstract
A memory system having first and second memory devices and a termination component. A first signal line is coupled to the first memory device to provide first data, associated with a write command, to the first memory device, and a second signal line coupled to the second memory device to provide second data, associated with the write command, to the second memory device. A control signal path is coupled to the first and second memory devices and the termination component such that the write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the termination component. A third signal line is provided to convey a clock signal that indicates when the write command propagating on the control signal path is to be sampled by the first and second memory devices.
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