Transversal filter circuit with a plurality of delay units, multiplexers, and full adders suited for a smaller decision feedback equalizer
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United States of America Patent
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Dec 4, 2012
Grant Date -
Feb 4, 2010
app pub date -
May 22, 2009
filing date -
Jul 31, 2008
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A transversal filter circuit comprises a plurality of delay units, a plurality of multiplexers and a plurality of full adders. The plurality of delay units is coupled in series to delay a two-bit input signal. The plurality of multiplexers is coupled to the plurality of delay units in a one-to-one manner, and outputs zero, a data signal, or the inverse of the data signal according to the output signals of the plurality of delay units. The plurality of full adders accumulates the outputs of the plurality of multiplexers and the MSB of the outputs of the plurality of the delay units.
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