Reconfigurable FADEC with flash based FPGA control channel and ASIC sensor signal processor for aircraft engine control
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Dec 4, 2012
Grant Date -
Mar 4, 2010
app pub date -
Aug 29, 2008
filing date -
Aug 29, 2008
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A reconfigurable FADEC includes a reconfigurable CPU configured for performing digital computing functions. A reconfigurable MSPD communicates with the CPU and is configured for performing analog I/O functions. A data bus is coupled to the CPU and the MSPD. The data bus is configured for connecting the CPU and the MSPD to an external connector.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully