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Abstract

An MD5 processing apparatus is a hardware-implemented MD5 process in a programmable device such as an FPGA or the like. The programmable device is programmed to include four processing engines, each of which performs a single MD5 stage having four MD5 operations performed by the MD5 stage. Each stage begins with four 32-bit values in an A register, a B register; a C register; and a D register. These values are processed using four sub-stages in the MD5 stage using a number of adders along with fixed nonlinear function processing units and fixed 32-bit-shift units. The fixed nonlinear function processing units in a given stage implement only the nonlinear function needed for the MD5 round being performed by the stage. Likewise, each fixed 32-bit-shift unit uses direct bit routing to effect bit shifts taking advantage of the cyclic nature of shifts required by the MD5 hashing algorithm.

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First Claim