Systems and methods for performing fixed-point fractional multiplication operations in a SIMD processor
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United States of America Patent
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Dec 11, 2012
Grant Date -
Mar 10, 2011
app pub date -
Sep 8, 2009
filing date -
Sep 8, 2009
priority date (Note) -
Expired
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Abstract
Systems and methods for performing multiplication of fixed-point fractional values with the same throughput as addition and subtraction operations, and without loss of accuracy in the result. In one embodiment, a method includes reading data from a pair of source registers that contains multiple single-width multiplicand values. Each multiplicand value in one of the source registers is paired with a corresponding multiplicand value in the other source register. For each pair of multiplicands, a double-width product is generated, then a single-width portion of the product is selected and stored in a target register. The selection of the single-width portion is performed by shifting the double-width products in funnel shifters. The immediate shifting of the double-width products to select the single-width portions allows the operation to achieve the same throughput as addition and subtraction operations.
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