Microchips with multiple internal hardware-based firewalls and dies
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United States of America Patent
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Dec 11, 2012
Grant Date -
Jan 29, 2009
app pub date -
Jun 30, 2008
filing date -
Nov 29, 1996
priority date (Note) -
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status (Latency Note)
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Abstract
A microchip comprising a first internal hardware-based firewall configured to deny access to a first portion of the microchip from a network; a general purpose microprocessor including two general purpose cores or general purpose processing units; at least two dies having been made by a separate fabrication processes and assembled into a package with separate die sections connected directly; and a memory component located inside of a second internal hardware-based firewall that is located between the memory component and one of the cores or processing units with which the memory component is associated. Wherein a first core is located within the first microchip portion protected by the first firewall; a second core is located within a second microchip portion not protected by the first firewall; and the second core is separated from the first core by the first firewall and is located between the first firewall and the network.
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