Clock signal generators having a reduced power feedback clock path and methods for generating clocks
Number of patents in Portfolio can not be more than 2000
United States of America
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Dec 18, 2012
Issued Date -
N/A
app pub date -
Apr 9, 2010
filing date -
Apr 9, 2010
priority date (Note) -
Withdrawn
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Abstract
Memories, clock generators and methods for providing an output clock signal are disclosed. One such method includes delaying a buffered clock signal by a adjustable delay to provide an output clock signal, providing a feedback clock signal from the output clock signal, and adjusting a duty cycle of the buffered clock signal based at least in part on the feedback clock signal. An example clock generator includes a forward clock path configured to provide a delayed output clock signal from a clock driver circuit, and further includes a feedback clock path configured to provide a feedback clock signal based at least in part on the delayed output clock signal, for example, frequency dividing the delayed output clock signal. The feedback clock path further configured to control adjustment a duty cycle of the buffered input clock signal based at least in part on the feedback clock signal.
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