Bit-erasing architecture for seek-scan probe (SSP) memory storage

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United States of America Patent

PATENT NO 8338813
APP PUB NO 20100080051A1
SERIAL NO

12631265

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Abstract

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An apparatus comprising a substrate, a heater formed on the substrate, and a phase-change layer formed on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer. A process comprising forming a heater on a substrate and forming a phase-change layer on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BLVD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chou, Tsung-Kuan Allen San Jose, US 32 342
Ma, Qing San Jose, US 250 7398
Rao, Valluri R Saratoga, US 68 1216

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