Blocking dielectric engineered charge trapping memory cell with high speed erase
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United States of America Patent
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Jan 1, 2013
Grant Date -
Aug 5, 2010
app pub date -
Apr 19, 2010
filing date -
Aug 9, 2007
priority date (Note) -
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Abstract
A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric.
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